Method and apparatus for adjusting phase of internal clock signa

Details Method and apparatus for adjusting phase of internal clock signa Method and apparatus for adjusting phase of internal clock signa

1997-04-08

1999-12-14

Ghebretinsae, Temesghen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

324161, 324243, H03D 324

Patent

active

060027320

ABSTRACT:
In a phase adjusting circuit, a signal generating circuit generates an internal signal based on an external signal and a feed-back signal. An output circuit outputs to a load circuit the internal signal having a first delay with respect to the generated internal signal from the signal generating circuit. A feed-back signal generating circuit delays the generated internal signal from the signal generating circuit by a sum of a second delay corresponding to the first delay and a third delay corresponding to a load of the load circuit, and outputs the delayed signal as the feed-back signal to the signal generating circuit.

REFERENCES:
patent: 5767715 (1998-06-01), Marquis et al.
patent: 5771264 (1998-06-01), Lane
patent: 5815016 (1998-09-01), Erickson
patent: 5852380 (1998-12-01), Yamauchi

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