Method and apparatus for adjusting overflow buffers and flow con

Details Method and apparatus for adjusting overflow buffers and flow con Method and apparatus for adjusting overflow buffers and flow con

1997-12-18

2000-07-04

Olms, Douglas W.

Multiplex communications

Data flow congestion prevention or control

Flow control of data transmission through a network

370253, 370422, H04J 116, H04L 100, H04L 1228

Patent

active

060848561

ABSTRACT:
A network switch having a shared memory architecture for storing data frames includes configuration registers that are programmable by a host processor to adaptively adjust overflow buffer locations and flow control watermark levels based on monitored network traffic. The host processor allocates shared resources by setting memory configuration registers corresponding to an external memory, where the network switch uses the external memory for storing received data frames, Management Information Base (MIB) counter values, and output port overflow data. The host processor periodically reads the MIB counter values from the external memory, and adjusts flow control watermark levels or the memory configuration registers in the network switch based on rate-based network traffic derived from the MIB counter values. PCI burst transfers between the host processor and the external memory via the network switch ensure that stored data is not lost during reconfiguration of the external memory. The disclosed arrangement enables resources used by the network switch to be adjusted to minimize congestion by borrowing resources from network ports serving idle stations.

REFERENCES:
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patent: 5822540 (1998-10-01), Caldara et al.
patent: 5956322 (1999-09-01), Charny
Lee Melatti, "Fast Ethernet: 100 Mbit/s Made Easy", Data Communications, vol. 23, No. 16, Nov. 1994, pp. 111-112, 114, 116.

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