Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-05-28
2000-03-07
Thai, Tuan V.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711104, 711167, 711154, G06F 1300
Patent
active
060353716
ABSTRACT:
An address for addressing a static random access memory based on a row address strobe signal, a row address, a column address strobe signal, and a column address, for addressing a dynamic random access memory, is determined by (a) latching, at a time based on the row (or column) address strobe signal, at least a portion of the row (or column) address to form latched address bits and (b) concatenating at least a portion of the column (or row) address and the latched address bits to form the address for addressing the static random access memory. A system including a static random access memory, a data bus coupled with the static random access.cndot.memory, an address bus, and a device coupled with the data bus and generating a row address strobe signal, a column address strobe signal, a row address applied to the address bus, and a column address applied to the address bus, may be provided with (a) a first address bus, coupling at least a portion of the address bus with a first portion of an address input of the static random access memory, (b) a second address bus, coupled with at least a portion of the address bus, (c) a third address bus, coupled with a second portion of the address input of the static random access memory, and (d) a latch having an input coupled with the second address bus, and an output coupled with the third address bus, and being responsive to an applied clocking signal which is based on one of the row address strobe signal and the column address strobe signal.
REFERENCES:
patent: 4755964 (1988-07-01), Miner
patent: 4901282 (1990-02-01), Kobayashi
patent: 4937791 (1990-06-01), Steele et al.
patent: 4975857 (1990-12-01), Katsura et al.
patent: 5025421 (1991-06-01), Cho
patent: 5187394 (1993-02-01), Hoshizaki et al.
patent: 5204841 (1993-04-01), Chappell et al.
patent: 5226011 (1993-07-01), Yanagisawa
patent: 5249160 (1993-09-01), Wu et al.
patent: 5249282 (1993-09-01), Segers
patent: 5257236 (1993-10-01), Sharp
patent: 5265218 (1993-11-01), Testa et al.
patent: 5299147 (1994-03-01), Holst
patent: 5321819 (1994-06-01), Szczepanek
patent: 5327317 (1994-07-01), Lee
patent: 5341486 (1994-08-01), Castle
patent: 5349565 (1994-09-01), Wu et al.
patent: 5438535 (1995-08-01), Lattibeaudiere
patent: 5835965 (1998-11-01), Taylor et al.
3Com Corporation
Michaelson Peter L.
Thai Tuan V.
LandOfFree
Method and apparatus for addressing a static random access memor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for addressing a static random access memor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for addressing a static random access memor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-372989