Method and apparatus for addressing a memory resource comprising

Details Method and apparatus for addressing a memory resource comprising Method and apparatus for addressing a memory resource comprising

1997-03-07

2000-11-28

Peikari, B. James

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

711220, G06F 1210

Patent

active

061548251

ABSTRACT:
A method and apparatus for accessing a memory resource, such as an array of DRAM modules, is described. The methodology commences with the receipt of a memory address during a memory access cycle. A row address is then generated by selecting predetermined bits of the memory address as the row address. Concurrently with the generation of the row address, a determination is made as to the configuration of a memory device within the memory resource and targeted by the memory address. Thereafter, a column address is generated by selecting bits of the memory address as the column address based on the configuration of the targeted memory device. The time required for the determination of the configuration of the targeted memory device is thus absorbed within the time expended generating the row address.

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