Method and apparatus for address translation pre-fetch

Details Method and apparatus for address translation pre-fetch Method and apparatus for address translation pre-fetch

2005-11-01

2005-11-01

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S204000, C711S213000, C710S052000, C710S056000

Reexamination Certificate

active

06961837

ABSTRACT:
An end of a queue or a page-crossing within a queue is detected. A virtual memory address for the head of the queue or for the next queue page is pre-translated into a physical memory address while the last entry in the queue or in the current queue page is being serviced.

REFERENCES:
patent: 5278963 (1994-01-01), Hattersley et al.
patent: 6611883 (2003-08-01), Avery
patent: 6742075 (2004-05-01), Bailey et al.
patent: 6789143 (2004-09-01), Craddock et al.
patent: 6813653 (2004-11-01), Avery
patent: 6831916 (2004-12-01), Parthasarathy et al.

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