Method and apparatus for address multiplexing to support variabl

Details Method and apparatus for address multiplexing to support variabl Method and apparatus for address multiplexing to support variabl

1997-03-07

2000-01-18

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

711217, G06F 1202

Patent

active

060165375

ABSTRACT:
Each of a plurality of output circuits is coupled with one pair of a plurality of pairs of adjacent odd and even bits of a sequential group of address bits. The output circuits provide an address bus with the odd address bits during a first time period and with the even address bits during a second time period. The odd address bits are provided as a column address (or a row address) and the even address bits are provided as the row address (or column address).

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patent: 5748977 (1998-05-01), Kawasaki et al.
Advanced Micro Devices, "Am186.TM.EM and Am188.TM.EM User's Manual with AM186 Instruction Definitions", 1995, pp. 1-1 thru 1-6; 2-1 thru 2-9; 3-1 thru 3-18; 4-1 thru 4-9; 5-1 thru 5-12; 6-1 thru 6-2; 7-1 thru 7-35; and 12-1 thru 12-6.
Advanced Micro Devices, "Am186.TM.EM and Am188.TM.EM High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers", 1996, pp. 29-48, 52-68, and 93-96.
Advanced Micro Devices, "AM186.TM.ES and AM188.TM.ES High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers", 1996, pp. 24-52, and 65-75.

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