Method and apparatus for address generation

Details Method and apparatus for address generation Method and apparatus for address generation

2007-06-19

2007-06-19

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S233100, C365S189011, C365S230060

Reexamination Certificate

active

11056048

ABSTRACT:
A system for generating one or more common address signals for multi-port memory arrays. The system includes circuitry receiving one or more read address signal; circuitry receiving one or more write address signal; circuitry receiving an array clock signal; circuitry receiving one or more enable signal; and circuitry generating the common address signals in response to the enable signal, the array clock signal and one of the read address signal and write address signal.

REFERENCES:
patent: 5668761 (1997-09-01), Muhich et al.
patent: 5943288 (1999-08-01), Jiang
patent: 6469953 (2002-10-01), Hong
patent: 6611469 (2003-08-01), Williams et al.
patent: 6657886 (2003-12-01), Adams et al.
patent: 6711664 (2004-03-01), Gold et al.
patent: 6741493 (2004-05-01), Christensen et al.
patent: 6760262 (2004-07-01), Haeberli et al.
patent: 6842373 (2005-01-01), La et al.
patent: 6963517 (2005-11-01), Chen
patent: 2005/0007813 (2005-01-01), Adams et al.

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