Method and apparatus for address FIFO for high-bandwidth...

Details Method and apparatus for address FIFO for high-bandwidth... Method and apparatus for address FIFO for high-bandwidth...

2006-08-01

2006-08-01

Bragdon, Reginald G. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C710S052000, C710S053000

Reexamination Certificate

active

07085880

ABSTRACT:
A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein the first read latch signal does not change the pointer location of the read pointer. A dynamic random access memory (DRAM) and system are also disclosed in accordance with the invention to include a FIFO buffer system to buffer memory addresses and commands within the DRAM until corresponding data is available.

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