Method and apparatus for address FIFO for high bandwidth...

Details Method and apparatus for address FIFO for high bandwidth... Method and apparatus for address FIFO for high bandwidth...

2011-03-22

2011-03-22

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C710S052000, C710S053000, C711SE12001

Reexamination Certificate

active

07913035

ABSTRACT:
A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein a first read latch signal does not change a pointer location of a read pointer. A dynamic random access memory (DRAM) and system are also disclosed in accordance with the invention to include a FIFO buffer system to buffer memory addresses and commands within the DRAM until corresponding data is available.

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