Method and apparatus for adaptive determination of timing...

Details Method and apparatus for adaptive determination of timing... Method and apparatus for adaptive determination of timing...

2007-05-15

2007-05-15

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S189070, C365S233100

Reexamination Certificate

active

11318952

ABSTRACT:
Methods and apparatus are provided for adaptive determination of timing signals, such as on a high speed parallel bus. The invention adaptively determines a timing signal having a first edge with respect to an internal clock, wherein the timing signal includes a period in which the timing signal is undriven, followed by a period immediately before a first transition in which the timing signal is in a predefined state. The timing signal is evaluated using one or more comparators; and an output of the one or more comparators are latched based on a clock signal. The clock signal is adjusted until the one or more comparators indicate the timing signal is in the known and valid state. The clock signal is further adjusted until the one or more comparators indicate the first transition has been reached. Thereafter, a gating control signal is established based on a timing of the first transition.

REFERENCES:
patent: 5062078 (1991-10-01), Arakawa
patent: 6889334 (2005-05-01), Magro et al.

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