Method and apparatus for adaptable burst chip select in a data p

Details Method and apparatus for adaptable burst chip select in a data p Method and apparatus for adaptable burst chip select in a data p

1996-06-06

1999-12-21

Nguyen, Hiep T.

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

710 34, 710130, G06F 926

Patent

active

060062886

ABSTRACT:
A data processing system (20) having a burst address generator (BAG) 55, with a programmable transaction mode applicable to both cache and pre-fetch architecture types. BAG 55 asserts a data acknowledge (DTACK) signal to end a burst transfer on either a physical boundary, as in pre-fetch mode at the end of a row in a memory device, or a limit detection, as in cache mode where the limit is determined by the length of a cache line. BAG 55 increments the burst address internally, and for operations in pre-fetch mode, the user determines if the incremented address is provided external to data processor (22).

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