Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-04-04
2006-04-04
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
07024511
ABSTRACT:
A system and method for peripheral control. The present invention relates to utilizing device address call sequencing for control of active memory bus peripheral devices. To prevent problems inherent with triggering events in active memory bus peripherals, such as are associated with error correction means, and to minimize pin usage, a system and method are provided to utilize memory address call sequencing of other devices to trigger such events.
REFERENCES:
patent: 4755932 (1988-07-01), Diedrich
patent: 5109333 (1992-04-01), Kubota et al.
patent: 5237616 (1993-08-01), Abraham et al.
patent: 5598575 (1997-01-01), Dent et al.
patent: 5687346 (1997-11-01), Shinohara
patent: 5818939 (1998-10-01), Davis
patent: 5862359 (1999-01-01), Nozuyama
patent: 5878240 (1999-03-01), Tomko
patent: 5960190 (1999-09-01), MacKenna
patent: 5999654 (1999-12-01), Toujima et al.
Emeka Mosanya et al., “CryptoBooster: A Reconfigurable and Modular Cryptographic Coprocessor”, Cryptographic Hardware and Embedded Systems, 1stInternational Workshop, 1999 proceedings, vol. 1717, Aug. 12, 1999, pp. 246-256.
Intel Corporation
Patel Nimesh
Perveen Rehana
Stutman-Horn Joni D.
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