Method and apparatus for achieving low power consumption...

Details Method and apparatus for achieving low power consumption... Method and apparatus for achieving low power consumption...

2006-10-17

2006-10-17

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S229000

Reexamination Certificate

active

07123522

ABSTRACT:
The present technique relates to a method and apparatus to provide a deep power down mode. In a memory device, such as DRAM or SRAM, various internal voltage buses provide power throughout the semiconductor chip. In a deep power down mode, grounding devices may be utilized to ground the internal voltage buses. With the internal voltage buses grounded, the outputs of the level shifters, which are control signals, may need to be forced into specific states. Through the use of the grounding devices and level shifters, leakage may be reduced and latch-up conditions may be reduced. As a result, the operation of the semiconductor chip may be enhanced because the problems associated with grounding the internal voltage buses may be diminished.

REFERENCES:
patent: 5831467 (1998-11-01), Leung et al.
patent: 6240028 (2001-05-01), Ho
patent: 6519707 (2003-02-01), Clark et al.
patent: 6552949 (2003-04-01), Silla et al.
patent: 6557090 (2003-04-01), Ho
patent: 6586979 (2003-07-01), Gomm et al.
U.S. Appl. No. 10/750,735, filed Dec. 31, 2003, Ho et al.
U.S. Appl. No. 10/231,509, filed Aug. 29, 2002, Gomm et al.
U.S. Appl. No. 09/815,465, filed Mar. 23, 2001, Gomm et al.

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