Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-04-08
1999-09-21
Canney, Vincent P.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
G06F 1100
Patent
active
059548304
ABSTRACT:
A method and apparatus for testing circuitry, such as a memory or a logic circuit, having a plurality of outputs, includes a built-in self-testing (BIST) test state machine for generating a plurality of address outputs, a plurality of multiplexers controlled by the address outputs of the test state machine, and a testing device for testing the plurality of outputs of the circuitry based on the address outputs of the test state machine. The plurality of outputs of the circuitry are input to the plurality of multiplexers and a number of outputs tested simultaneously is less than a total number of outputs of the circuitry.
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Canney Vincent P.
International Business Machines - Corporation
Walter Jr., Esq. Howard J.
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