Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-02-03
2003-07-15
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S401000, C257S797000
Reexamination Certificate
active
06593168
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method and system for accurate alignment of integrated circuits in a flip-chip configuration.
2. Description of the Relevant Art
Fabrication of integrated circuits upon semiconductor wafers involves numerous processing steps. For example, the fabrication of a metal-oxide-semiconductor (“MOS”) integrated circuit includes the formation of trench isolation structures within a semiconductor wafer, generally a silicon wafer, to separate each MOS field-effect transistor (“MOSFET”) that will be made. The wafer is typically doped with either n-type or p-type impurities. A gate dielectric, typically composed of silicon dioxide, is formed on the surface of the wafer. For each MOSFET being made, a gate conductor is formed over the gate dielectric and a source and drain are formed by introducing dopant impurities into the wafer. Conductive interconnect lines are then formed to connect the MOSFETs to each other and to the terminals of the completed integrated circuit. Modern high-density integrated circuits typically include multiple interconnect levels to provide all of the necessary connections. Multiple interconnect levels are stacked on top of each other with intervening dielectric levels providing electrical insulation between interconnect levels.
During manufacture of an integrated circuit (e.g., a microprocessor), interconnect lines formed upon a wafer which are to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads (these pads are also referred to as “bonding pads” herein). Following manufacture, the integrated circuit is typically secured within a protective semiconductor device package. In addition to providing mechanical, electromagnetic, and chemical protection for the circuit, a package typically provides connections between the circuit and a printed circuit board to which it is attached, and may also assist with dissipation of heat from the circuit. Some types of device packages have terminals called “pins” for insertion into holes in a printed circuit board. Other types of device packages have terminals called “leads” for attachment to flat metal contact regions on an exposed surface of a printed circuit board. Each bonding pad of a circuit to be packaged is connected to one or more contact pads on the IC-mounting, or “mounting” surface of the device package (typically the side of the package opposite the side connected to the circuit board). Traditionally the contact pads of device packages have been arranged about the periphery of the package, and bonding pads of a circuit have been arranged at the periphery of the circuit. Fine metal wires are typically used to connect the bonding pads of the circuit to the contact pads of such a device package, in a process known as wire bonding.
More recently, a different packaging geometry known as “flip chip” packaging is increasingly employed. A flip chip as used herein is an integrated circuit (also called a “chip” or “die”) mounted onto a substrate in such a way that the processed surface of the circuit (the surface upon which the transistors are formed, as opposed to the back side of the circuit) is facing the substrate onto which the circuit is mounted. In other words, a flip chip is mounted onto a substrate “upside down” as compared to a wire-bonded circuit, which is said to be in a “die-up” configuration. Similarly, circuits mounted in a flip-chip geometry are also said to be in a “die-down” configuration. Several features of the flip-chip packaging configuration make it attractive for packaging of high-performance circuits. A commonly used flip chip technology is the solder-bumped flip-chip technology, also known as “controlled-collapse chip connection”, or “C4”. In this process, solder bumps or balls are formed on the bonding pads of the circuit. The bumps are placed in contact with the corresponding contact pads of the substrate to which the circuit is to be mounted, and heat is applied to form solder connections to mount the circuit to the substrate. Unlike the wire-bonding process, formation of solder bumps may be done on bonding pads arranged above active areas of a circuit without damaging the underlying circuitry. Bonding pads for flip-chip packaging may therefore be arranged in a two-dimensional array across the integrated circuit, rather than being limited to the periphery of the circuit. The circuit, or die, may itself therefore be smaller than a comparable wire-bonded circuit. Similarly, the flip-chip mounting of the circuit onto a substrate allows the contact pads on the substrate to be directly aligned with the corresponding bonding pads on the circuit, rather than outside the periphery of the circuit as with wire-bonded packaging. The size of the package is therefore also reduced as compared to the package needed for a wire-bonded circuit. This reduced die and package size reduces overall integrated circuit cost. Furthermore, flip chip packaging generally provides improved electrical performance as compared to wire-bonded packaging, because the solder connections are shorter than wire bonds and typically exhibit reduced resistance, capacitance and inductance.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modem day processes employ features, such as gate conductors and interconnects, which have less than 0.3 &mgr;m critical dimension. As feature size decreases, the sizes of the resulting transistors as well as those of the interconnects between transistors also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area. This reduction in transistor size necessitates more bonding pads on a circuit for a given die size, and this in turn may cause smaller bonding pads to be required. Various factors may limit the quantity and size of bonding pads on the integrated circuit (and of the corresponding pads on the substrate). For example, the size of a bonding pad may be limited by how small the solder bump formed on the bonding pad can be made. Furthermore, the spacing between bonding pads may be limited by space needed for thermal expansion of the solder connections during the thermal cycling which occurs during packaging, testing and operation of the integrated circuit.
The size and/or spacing of bonding pads could also be limited by the alignment accuracy achievable when connecting the bonding pads to the corresponding contact pads on the substrate. Such alignment accuracy has not historically been considered extremely important in flip-chip packaging, because the bonding pad density has been small enough that alignment requirements have not been severe. For example, the pitch of a bonding pad array used in a current C4 process may be as large as 100 microns or greater. “Pitch” as used herein refers to the distance between a point on an element in an array (such as an bonding pad or contact pad) and the corresponding point on an adjacent element in the array. For example, the center-to-center distance between adjacent bonding pads in an array corresponds to the pitch of the array. In addition to the relatively large bonding pad spacings used historically, flip-chip solder bump connections benefit from a self-alignment property of the solder connection. Because the solder preferentially “wets” the metal bonding pads and contact pads as opposed to the surrounding insulator, the surface tension of the solder tends to move the chip into alignment over the substrate during the heating process which forms the connections between the bonding pads and the contact pads on the substrate, as long as there is some initial overlap between the solder bump on the bonding pad and the metal contact pad.
As integrated circuit features continue to get smaller, however, it is believed that current limi
Ehrichs Edward E.
Kirsch Travis D.
Wooten Chris L.
Kowert Robert C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Picardat Kevin M.
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