Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1998-01-26
2001-09-11
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S207000
Reexamination Certificate
active
06289431
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory management in a computer system, and more specifically, to a method and apparatus for providing paged memory in the computer system.
BACKGROUND OF THE INVENTION
As memory paging schemes have developed, certain formats have been frequently used. For example, one common paging scheme is to have up to 4 Gigabytes of memory divided into multiple 4-kilobyte pages. Directory entries and page table entries in such a scheme are 4-byte (32-bit) entries having a base address and multiple control bits that indicate permissions. For 16- and 32-bit processors, such a scheme is sufficient.
For many years operating systems have been written for paging schemes with 4-byte table entries and 4-kilobyte pages. However, processors that can address more than 4 Gigabytes of memory have been developed, and for these processors, providing more than 4 Gigabytes of memory with 4-kilobyte pages requires table entries of more than 4 bytes. Table entries of more than 4 bytes are used for memories larger than 4 Gigabytes because the formats used for 4 Gigabyte and smaller memories do not have enough bits available to support the larger addresses of memories larger than 4 Gigabytes in size.
Because many operating systems have been designed based on 4-kilobyte pages and 4-byte table entries, these existing operating systems cannot take advantage of memory beyond 4 Gigabytes. Therefore, what is needed is a memory paging system having 4-byte table entries and 4-kilobyte pages that can access more than 4 Gigabytes of physical memory. The present invention provides a memory paging system that accesses more than 4 Gigabytes of memory while maintaining 4-kilobyte pages. Thus, modifications to existing operating systems to access memory beyond 4 Gigabytes are greatly reduced compared to a memory paging systems having table entries larger than 4 bytes.
SUMMARY OF THE INVENTION
A method and apparatus for accessing paged memory having two page sizes with a processor is described. A processor and memory are coupled to a bus. The processor accesses memory via a paging system having two page sizes. In one embodiment, pages in memory up to 64 Gigabytes in size are accessed via 4-byte table entries. In another embodiment, pages of one of the two page sizes are accessed by a page directory entry and a page table entry where the page table inherits permissions from the page directory entry.
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Bigbee Bryant E.
Hacking Lance E.
Shahidzadeh Shahrokh
Thakkar Shreekant S.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Hiep T.
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