Active solid-state devices (e.g. – transistors – solid-state diode – Superconductive contact or lead – Transmission line or shielded
Reexamination Certificate
2003-03-04
2004-08-24
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Superconductive contact or lead
Transmission line or shielded
C257S678000, C257S691000, C257S698000, C257S048000, C438S015000, C438S017000, C438S018000
Reexamination Certificate
active
06781218
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of testing integrated circuits. More specifically, embodiments of the present invention relate to accessing internal nodes of flip-chip packaged integrated circuits to measure voltage transitions at the nodes.
2. Prior Art
Measurements of voltage transitions at internal circuit nodes are needed during the development and testing of complex integrated circuits (“ICs” hereafter). A circuit node is any point on the electrical connections of the IC (e.g., an input or output terminal of a logic gate). Despite use of sophisticated simulation tools, many ICs still fail to operate as designed, and diagnostic procedures must be undertaken to determine the cause of the failure. In some instances, mechanical probing and beam (electron beam) probing provide the requisite information. However, when the well-known flip-chip packaging (the die being mounted face down to its package substrate) technology is used, micro-mechanical and electron beam probe access to the principal (metal connection) side of the IC die is blocked.
It is known to use a light beam to measure voltage at an internal node in a conventional flip-chip packaged IC. An example of a conventional system for measuring circuit voltage at an internal node of an IC using light is IDS2000 manufactured by Schlumberger, and described in U.S. Pat. No. 5,905,577. To access the internal circuit elements, first the IC die is stripped of the package to expose the metal connection side of the IC die. A light beam is focused on a circuit element of the IC, such as a diode where the measurements are desired in the IC, from the metal connection side of the IC die.
A test program generating a series of commands (e.g., test patterns) is run on the IC, the test patterns are applied to the input pins of the IC. In response to the past patterns (vectors), voltage transitions take place at the circuit node, which is merely a point on an electrical connection to the circuit element. The light reflected from the circuit element, electrically connected to the circuit node, is modulated by changes in the electrical state of the node in response to the test patterns. Thus the reflected light provides a measure of voltage transitions (signals) at the node.
There are drawbacks associated with using this method to test integrated circuits. First, the modulation of the reflected beam is very weak and averaging techniques must be used to obtain low noise measurement waveforms. Second, many IC faults are intermittent, (e.g., in logic circuits) so that averaging will produce false results unless the IC activity is exactly repeated for every test pattern
Access to such internal circuit nodes can be achieved by providing an on-chip circuit called a scan chain The test method modifies the otherwise conventional flip-flops used in the IC, providing a two input data selector to the D input terminal of each flip-flop. The data selector control signal for all the flip-flops is a common signal called Scan Enable. With Scan Enable, in the low logic state, the data selector is set for normal IC operations. However, the Q output terminal of each flip-flop is coupled to the normally unused data selector input of another flip-flop. When Scan Enable is in the high logic state, this path is enabled, forming a continuous shift register structure from all the modified and connected flip-flops. By this means, serial data representing an arbitrary logic state can be loaded from one of the IC input pins into the shift register with Scan Enable high, and normal IC operation begun from this arbitrary internal state by switching Scan Enable low. Also at any point in the normal operation of the IC, Scan Enable can be made logic high, thus latching the logic state for all internal nodes into the shift register. The contents of the shift register can then be clocked to an output pin for analysis. For a detailed description of scan test methods, see Alfred L. Crouch, “Design For Test For Digital ICs And Embedded Core Systems,” Prentice Hall, 1999.
However, the scan chain operations cannot be performed at full device operating speed. The internal scan chain can give accurate information to the IC logic state only when the associated processor clock is stopped. Thus at low speed all faults may be located, but faults occurring only at high speed may elude isolation in time and position. Latching of the scan chain can be done with the DUT (device under test, referring to the IC under test) operating at full clock speed, thereby obtaining a “snap shot” of the IC internal nodes at an instant of time. However, it is difficult to distribute simultaneously to the scan chain the latching lock pulse, or at least distribute the latching clock pulse within a small fraction of the device clock speed. Because of this, the data obtained in this manner is suspect. The on-chip time relationship between voltage transitions on two nodes is not accurately represented in the data obtained in this manner. This skew distribution problem becomes worse as the number of active circuits contained in a DUT increase.
Thus, it would be desirable to provide access to circuit nodes of a DUT to obtain reliable measurements of faults occurring at high speed. It would also be advantageous to provide signal outputs to an associated printed circuit board from internal circuit nodes for diagnostic purposes. However, the incremental cost of providing these connections will be very high, because a larger surface area package will be needed, and the difficulty of routing all the connections on the printed circuit board would be increased. This cost would have to be borne by every IC produced, even after the diagnostic process had been completed and the extra no longer needed. Hence, this would not be economical.
SUMMARY OF THE INVENTION
Accordingly, what is needed is a solution to the problems associated with conventional IC testing. The present invention provides access to the electrical state of the internal nodes of an IC DUT.
The well-known flip-chip method of packaging ICs has greatly increased the available number of electrical connections between the IC die and the associated mounting substrate of the IC package. (“Package” in the IC field refers to the plastic or ceramic housing for the die and its associated electrical leads.) In an integrated circuit, in accordance with an embodiment of the present invention, each electrical connection between the IC die and the top of the package substrate is made by a deformable “ball bond.” The ball bonds can be made anywhere on the IC die surface; they are not constrained to the edge of the die. The package substrate is a multi-layered polyimide or ceramic structure, containing power planes (conductors) and impedance controlled signal transmission lines. The package substrate power planes and signal transmission lines are coupled by interlayer vertical connections (vias) to a flat pad or a pin on the bottom layer of the package substrate. The pads or pins are used conventionally to make electrical connections to the associated printed circuit board on which the package IC is mounted. A number of the ball bonds are used for power and ground connections to the substrate, so that the high current required by the IC is carried by many such bonds. The number of ball bonds may exceed, e.g., two thousand and hence many are also available to carry signals from internal nodes of the IC to the multi-layered package substrate.
In one embodiment a circuit internal node on the IC is coupled to a buffer on chip to drive the node's signal onto a path including an associated ball bond and a trace (conductor) that Is terminated in a pad on the top (principal) surface of the package substrate. An example of a buffer (amplifier) is an inverter. The pad is located beyond the edge of the die, thereby, being readily accessible by the test apparatus and is not used as a signal path for normal IC operations. There is sufficient space around the edges of the IC die on the top surface of a typical sized
Flynn Nathan
Forde Remmon R.
NPTest Inc.
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