Method and apparatus for accessing graphics cache memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Details

C711S129000, C711S147000, C711S151000, C711S152000, C711S153000, C711S130000

Reexamination Certificate

active

06173367

ABSTRACT:

FIELD OF THE INVENTION
The present application relates generally to the use of a cache memory, and more specifically relates to a method and apparatus for accessing a video data cache memory.
BACKGROUND OF THE INVENTION
Computers are known to include a central processing unit, audio processing circuitry, peripheral ports, video graphics circuitry, and system memory. Video graphic controllers, which include cache memory, are utilized in computers to process images for subsequent display on a display device. Display devices include computer monitors, televisions, liquid crystal display panels, and any other device capable of visually displaying pixel information. The cache memory is used to improve performance of computer systems by temporarily storing data in memory devices that allow for high- speed data access as compared to data retrieved from other lower speed memory devices such as system memories, disks, or tapes. Cache memory is generally used as temporary storage for recently or frequently used data. The use of cache memories allow data processors to access data at a higher rate than that generally available through memories associated with the systems. This avoids the latency times associated with accessing low speed memories.
Current video graphic systems need to support both two-dimensional (2D) and three-dimensional (3D) applications. Generally, memory supporting 2D graphics, including cache memories, would be mapped such that there would be a direct relationship between pixel location and memory location. For example, two 8-bit bytes could be used to represent a single pixel, or a single 128-bit word could be used to represent 8 adjacent pixels, each pixel having two bytes of associated memory. A system optimized to support 2D graphics would generally have a single cache with two or more, independent ports, wherein recent direct mapped memory accesses could be stored. However, a system optimized for 2D graphics application would not necessarily be advantageous for a 3D graphics application.
3D graphics applications add additional dimensions of complexity to the video controller in order to quickly calculate 3D images. Each visual element associated with 3D graphics needs not only its 3D shape information, but additional shading information, or Z data, reflection information, and the Z-plane information. For example, the Z-plane information represents the plane where a specific element is with reference to other elements being rendered. For example, if a person and a house were to be illustrated in 3D form, it is necessary to know whether or not the person is standing in front of the ouse or behind the house. This information is carried by Z data information.
Z data information is used by the graphics engine in order to determine what lements are actually visible on the monitor. Once the Z data information, and other 3D information, has been used to determine what will be displayed on the monitor, it is possible to write data associated with those items that are to be displayed to a direct mapped memory location. In fact, handling Z data information as well as displaying pixel information are two very memory-intensive processes in the rendering pipeline.
This is different than the nature of 2D graphics which have a significant percentage of “copy” operations, which can be broken down into a read process and display process, wherein a clients perform read and writes to memory. In 3D applications, speed is optimized if each process is treated as a separate client and has its own dedicated port to the cache.
Therefore, it would be desirable to have a video cache capable of supporting the requirements of both 2D graphics and 3D graphics.


REFERENCES:
patent: 5043874 (1991-08-01), Gagliardo et al.
patent: 5392405 (1995-02-01), Komatsu et al.
patent: 5581734 (1996-12-01), DiBrino et al.
patent: 5689656 (1997-11-01), Baden et al.
patent: 5974506 (1999-10-01), Sicola et al.

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