Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2007-06-12
2007-06-12
Mai, Son L. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189011
Reexamination Certificate
active
11081870
ABSTRACT:
The invention relates to accessing contents of memory cells. Some embodiments include a memory structure that has a first cell, a second cell, and a sense amplifier. The first cell stores a first value. The first and second cells are connected to the sense amplifier by one or more bit lines. The sense amplifier receives the first value stored by the first cell by using the one or more bit lines and drives the received first value to the second cell through the one or more bit lines. The receiving and driving occur in a single clock cycle. In some embodiments, the second cell outputs the first value. The memory structure of some embodiments also includes a third cell connected to the sense amplifier by the one or more bit lines. The sense amplifier drives a second value to the third cell while the second cell outputs the first value. Other embodiments include a method for accessing data in a memory structure. The method receives a value stored by a first cell; and drives the received value to a second cell. The receiving and driving occur in a single time period. In some embodiments, the method also includes driving a first value to the second cell in a first time period and driving a second value to a third cell in a second time period. In these embodiments, the second cell outputs the first value during the second time period and the third cell outputs the second value during a third time period.
REFERENCES:
patent: 5245575 (1993-09-01), Sasaki et al.
patent: 5369622 (1994-11-01), McLaury
patent: 5532958 (1996-07-01), Jiang et al.
patent: 5768178 (1998-06-01), McLaury
patent: 6111779 (2000-08-01), You
patent: 6134154 (2000-10-01), Iwaki et al.
patent: 6173379 (2001-01-01), Poplingher et al.
patent: 6205076 (2001-03-01), Wakayama et al.
patent: 6326651 (2001-12-01), Manabe
patent: 6724648 (2004-04-01), Khellah et al.
patent: 6809979 (2004-10-01), Tang
patent: 6903962 (2005-06-01), Nii
patent: 6925025 (2005-08-01), Deng et al.
patent: 6937535 (2005-08-01), Ahn et al.
patent: 6970374 (2005-11-01), Lin
patent: 7027346 (2006-04-01), Houston et al.
patent: 2001/0038552 (2001-11-01), Ishimaru
patent: 2004/0233758 (2004-11-01), Kim et al.
patent: 2005/0128789 (2005-06-01), Houston
U.S. Appl. No. 11/081,874, filed Mar. 15, 2005, Redgrave.
U.S. Appl. No. 11/081,874, filed Mar. 15, 2005, Redgrave.
“Design for Low Power in Actel Antifuse FPGAs”, Actel Application Note, 2000 Actel Corporation, Sep. 2000, pp. 1-8.
Gayasen, A., et al., “Reducing Leakage Energy in FPGAs Using Region-Constrained Placement,”FPGA '04,Feb. 22-24, 2004, pp. 51-58, ACM, Monterey, California, USA.
Redgrave Jason
Schmit Herman
Mai Son L.
Stattler Johansen & Adeli LLP
LandOfFree
Method and apparatus for accessing contents of memory cells does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for accessing contents of memory cells, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for accessing contents of memory cells will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3883034