Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-02-21
2006-02-21
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C703S013000, C703S023000
Reexamination Certificate
active
07003746
ABSTRACT:
A method and system for accelerating software simulator operation with the aid of reprogrammable hardware such as Field Programmable Gate Array devices (FPGA). The method and system aid in emulation and prototyping of Application Specific Integrated Circuits (ASIC) digital circuit designs by means of reprogrammable devices. The system includes a design verification manager and software program that includes subroutines of finding clock sources, finding synchronous primitives that are receiving clock signals from the clock sources, and a subroutine for inserting edge detector circuits between such clock sources and synchronous primitives. This new method allows eliminating of clock timing issues by applying basic design clocks to the clock enable instead of clock trigger inputs and generating and applying to clock trigger inputs a new clock that is automatically delayed in respect to all other clocks in the design. This system solves the major obstacle for automatic retargeting of ASIC designs into reprogrammable devices that have different timings of the clocking chains in ASICs and FPGAs that result in triggering of associated flip-flops and latches at different times.
REFERENCES:
patent: 5475830 (1995-12-01), Chen et al.
patent: 5579510 (1996-11-01), Wang et al.
patent: 6009256 (1999-12-01), Tseng et al.
patent: 6009531 (1999-12-01), Selvidge et al.
patent: 6301553 (2001-10-01), Burgun et al.
patent: 6389379 (2002-05-01), Lin et al.
patent: 2003/0105617 (2003-06-01), Cadambi et al.
Grabowski Slawomir
Hyduke Stanley M.
Garbowski Leigh M.
Trojan Law Offices
LandOfFree
Method and apparatus for accelerating the verification of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for accelerating the verification of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for accelerating the verification of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3712213