Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing
Reexamination Certificate
1998-04-08
2001-08-14
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Addressing
C345S503000, C345S531000, C345S565000, C711S202000
Reexamination Certificate
active
06275243
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field Of The Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for varying the arrangement of frame buffer memory to increase the speed of vertical access.
2. History Of The Prior Art
A frame buffer provides storage for pixel data which is to be displayed on a computer output display. Frame buffer memory is conventionally two dimensional dynamic random access memory or some modification thereof. Frame buffer memory is of some fixed size in each of the two dimensions. The size is selected as a compromise to best handle the various display formats which may be presented on an output display. Pixel data describing a frame is stored linearly in a frame buffer beginning at the start of some first row, continuing through that row to the end, starting again at the beginning of the next row, and continuing this pattern to the end of the last row of the memory array.
Data is transferred to a frame buffer by addressing rows and columns. When a sequence of data is being placed in different columns of the same row of a frame buffer, the time required to switch between columns is usually only a single cycle. This occurs because column selection requires only selecting a different accessing address using a multiplexor. However, when accessing a frame buffer, the time required to switch between rows is typically ten cycles. This occurs because the operation requires charging of capacitors involved in row select operations.
With linear memory storing pixel data, selection of a different column proceeds rapidly while of a different row is very time consuming. This is satisfactory for frame buffer clearing which takes place linearly. Graphics operations, however, require as much vertical as horizontal movement. Therefore, the arrangement of frame buffers causes graphics operations to proceed slowly.
It is desirable to increase the speed of graphics operations in computers.
Summary Of The Invention
This and other desirable results of the present invention are realized by a circuitry and a method for rearrangement the storage of pixel data in frame buffer memory so that movement in the vertical direction on an output display requires less movement between pages in the physical memory used for the frame buffer. This is accomplished by circuitry which rearranges addressing to physical memory to place pixel data in positions where it is less likely that vertical movements will require page boundary crossings.
These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.
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Lim Raymond
Priem Curtis
Chauhan Ulka J.
Girard & Equitz LLP
Nvidia Corporation
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