Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-03-30
2004-11-16
Beausoliel, Robert (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S016000
Reexamination Certificate
active
06820216
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer systems and, more particularly, to a method and apparatus by which a computer processor may accelerate fault handling.
2. History of the Prior Art
A computer processor continually encounters circumstances in which it must halt the processing of a particular sequence of instructions to attend to some occurrence not usually encountered in the sequence. These occurrences are variously referred to as errors, exceptions, faults, and other terms which are often defined differently by different parties and under different circumstances. In general, such occurrences all require the processor to halt the sequence of instructions it is presently processing and take some action outside of the execution of the interrupted sequence.
As one example, an error in executing a particular sequence may require that the processor stop the execution, discard the results generated to that point, and move back to an earlier point in the sequence to begin reexecution. On the other hand, an interrupt may be generated by a modem signaling that data is arriving from circuitry external to the computer that is executing the sequence. Such an interrupt may require the processor to stop execution of the sequence, receive the externally-provided data, and then return to executing the sequence at the point at which it was stopped. There are many other situations in which a processor must halt its processing in order to attend to matters outside of the execution of an executing sequence, and all are subject to a number of the same difficulties. Because there are many different situations, in this specification, the use of each of the terms fault, exception, error, and the like is intended to encompass all of these terms except where otherwise stated or made obvious from the text.
The typical method of handling exceptions is to interrupt the sequence of instructions being executed, save enough information about the sequence and its execution up to its interruption to be able to return to the sequence and continue its execution, then transfer control of the processor to a software sequence of instructions for handling the exception (usually referred to as an exception handler), execute the exception handler to handle whatever needs be done to take care of the exception, retrieve the information about the interrupted sequence and its execution up to its interruption, and recommence execution of the interrupted sequence of instructions. Of course, in many situations, the exception will be such that the interrupted sequence cannot or should not continue so that the processor will be directed to some other sequence of instructions by the handler.
In those situations in which the proper action for the processor is to return to the interrupted sequence and continue its execution, it is necessary for the processor to understand at what point the interruption occurred so that execution may recommence at the proper point in the sequence.
In many situations, even though a typical processor will have stored information sufficient to be able return to the point of interruption, it may not know the exact point in the sequence to which it should return and will have to compute this point. For example, when a process is interrupted in order to allow another process to execute, then it is necessary for the interrupt to take effect at a point at which consistent state exists. However, a processor executing a speculative sequence of instructions will probably not commit to memory information generated by the speculative sequence until the sequence is determined to be the proper sequence for execution and has executed without error. Thus, if execution of a speculative sequence is interrupted, the interrupt may not occur at a point at which consistent state exists because information from the interrupted sequence has not yet been stored. Thus, the point at which the sequence is actually interrupted might not be a point at which consistent state exists and at which a new sequence may begin. Although the processor knows where the interrupt occurred, the processor may have insufficient information to immediately return to a point at which consistent state exists. In such a case it is necessary for the processor to use what data it has to determine a correct point to recommence execution. A significant amount of time and storage is often required to accomplish this determination, especially where subroutines are involved in the interrupted sequence.
It is desirable to provide circuitry and processes by which a processor may determine a point to recommence execution of an interrupted sequence of instructions more quickly than by using prior art techniques.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to enhance the operation of a microprocessor by providing improved methods and circuitry for accomplishing fault handling.
This and other objects of the present invention are realized by a process which stores an indication of a next instruction in a sequence of instructions which is to be executed whenever during execution of instructions of the sequence it is apparent that state of the process is consistent, and refers to the stored indication to determine an instruction to which to return from handling a fault.
These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.
REFERENCES:
patent: 3736566 (1973-05-01), Anderson et al.
patent: 4740969 (1988-04-01), Fremont
patent: 5043866 (1991-08-01), Myre et al.
patent: 5524205 (1996-06-01), Lomet et al.
patent: 5958061 (1999-09-01), Kelly et al.
patent: 5974425 (1999-10-01), Obermarck et al.
patent: 6011908 (2000-01-01), Wing et al.
patent: 6105148 (2000-08-01), Chung et al.
patent: 6185702 (2001-02-01), Shirakihara et al.
patent: 6480944 (2002-11-01), Bradshaw et al.
patent: 6662311 (2003-12-01), Itoh et al.
patent: 2002/0032883 (2002-03-01), Kampe et al.
Tanenbaum, Andrew Structured Computer Organization (2ndEdition 1984) excerpt.
Cmelik Robert
Wing Malcolm
Beausoliel Robert
Bonzo Bryce P.
Transmeta Corporation
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