Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-11-16
2002-09-24
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S016000, C710S011000, C710S105000
Reexamination Certificate
active
06457086
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains generally to speed signal detection in serial bus device communication. More particularly, the invention is a method and apparatus for accelerating detection of speed code signals, and in particular S
400
signals in IEEE Standard 1394-1995, to thereby reduce the bottleneck through physical layer services of a serial bus device.
2. The Prior Art
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) defines the IEEE Standard 1394-1995 serial bus architecture in the document “IEEE Standard for a High Performance Serial Bus” published Aug. 30, 1996 which is incorporated herein by reference. In IEEE 1394, the serial bus architecture is defined in terms of nodes. In general, a node is an addressable entity (i.e., a logical entity with a unique address), which can be independently reset and identified.
The IEEE Standard 1394-1995 further describes a set of three stacked layers comprising a transaction layer, a link layer (LINK), and a physical layer (PHY). Interoperability between the serial bus nodes begins with the physical connection, typically through cables, connectors, and PHY silicon.
The PHY has three primary functions: transmission and receptions of data bits, arbitration, and provision for the electrical and mechanical interface. Transmission of data bits is carried out using the transmission format
1
depicted in FIG.
1
. The transmission format
1
includes a data prefix
2
and a data packet
3
.
For every data packet
3
that is transmitted, the data packet
3
is preceded by a data prefix
2
. The data packet
3
may vary in size according to the data transmitted. For example, the data packet may be 8 kilobits (Kb) at S
100
speeds (or 32 Kb at S
400
speeds).
The data prefix
2
communicates, among other things, a speed code signal to indicate the data rate of transmission. The cable environment supports multiple data rates of 98.304 megabits per second (Mb/s) or S
100
, 196.608 Mb/s or S
200
, and 393.216 Mb/s or S
400
. The lowest speed (S
100
) is known as the “base rate”. If a higher rate is supported then all lower rates also required.
Speed signaling (also known as common mode signaling) is carried out by indicating an analog signal, and in particular, a common voltage drop (V
cm
) across the Twisted Pair B (TPB) interface of the cable media as is known in the art. As noted above, this speed code signal is communicated during the data prefix
2
portion of the data transmission
1
. In general, the speed code signal communicated during the data prefix
2
must be completed 40 nanoseconds (ns) before the data packet
3
portion.
FIG. 2
a
and
FIG. 2
b
illustrate generally speed code signals communicated by the PHY devices as described above.
FIG. 2
a
illustrates an S
200
speed code signal
4
to indicate the S
200
data rate.
FIG. 2
b
illustrates an S
400
speed code signal
5
to indicate the S
400
data rate. The base rate (S
100
) is indicated by a lack or absence of a speed signal code signal during the data prefix
2
.
The S
200
speed code signal
4
and the S
400
speed code signal
5
are generally 100 ns in length. However, the S
200
speed code signal
4
indicates a V
cm
drop of about 140 millivolts (mV). In contrast, the S
400
speed code signal
5
indicates a V
cm
drop of about 450 mV. The details of implementing speed signal reception was largely left to the designer of a PHY to provide the necessary filtering algorithm that ascertains the various speed code signals communicated by the other PHY devices on the serial bus.
Referring now to
FIG. 3
there is generally shown a “driver blast” signal
6
which may sometimes be indicated during the data prefix portion
2
of the data transmission
1
. This driver blast signal
6
may sometimes arise when the output of differential port drivers are not activated simultaneously, thereby creating a V
cm
drop of about 140 mV generally lasting no more than 10 ns.
The problem created by the driver blast signal
6
is that the V
cm
drop of the driver blast signal
6
appears like and has a similar slope and amplitude to the V
cm
drop of an S
200
speed code signal
4
. The difference between the two signals is the length of the signal, the S
200
speed code signal
4
lasting about 100 ns while the driver blast signal
6
generally lasting no longer than 10 ns. To distinguish between the driver blast signal
6
and the speed code signals
4
,
5
, and to avoid misinterpreting the driver blast signal
6
for a speed code signal, a proposed speed filter algorithm has been provided in Table 8-21 of the P1394a Draft 4.0 (most recent), published by the IEEE in Sep. 15, 1999 and is incorporated herein by reference. Many current PHY devices implement this speed filter algorithm.
This proposed speed filter algorithm is represented in flow chart form in FIG.
4
. In general, signals are sampled at 20 ns intervals. According to the algorithm, if two consecutive S
200
signals (i.e., V
cm
drop level to that of an S
200
speed code signal) are observed then S
200
mode is determined to be valid. Similarly, if two consecutive S
400
signals are observed, then S
400
mode is determined to be valid. Otherwise S
100
mode is the default mode. By requiring two consecutive signals, both of S
200
or both of S
400
, the driver blast signal
6
can be filtered out because two consecutive samples requires the necessary V
cm
signal for a 20 ns period minimum, whereas the V
cm
produced by the driver blast signal
6
generally lasts no more than 10 ns.
As shown in
FIG. 4
, it is common to first detect the S
200
signal
4
before detecting the S
400
signal
5
, primarily due to the slope of the S
400
signal. This is because the leading edge of an S
400
speed signal is a somewhat leisurely drop to S
400
levels; it spends considerable time transitioning through S
200
range. In general, the total propagation delay (bottleneck) of a signal through a PHY device is generally 130 to 140 ns, a portion of which is dedicated to sampling speed codes. For detection of S
400
speed signals for example, the prior art algorithm described above may not determine the validity of an S
400
speed signal until as late as 60 ns (20 ns for sampling the S
200
signal, plus 40 ns for sampling two consecutive S
400
signals). It is noted that for detection of S
200
speed signals, the prior art algorithm described above consumes about 40 ns (two consecutive samples at 20 ns each) for sampling signal. Thus, the propagation delay for detecting S
400
signals will generally be greater than the propagation delay for detecting S
200
signal.
It is observed that the V
cm
drop level produced by the driver blast
6
does not reach the V
cm
drop level produced by an S
400
speed code signal
5
. Thus, for S
400
speed code signaling, filtering for driver blast
6
is not generally required. The prior art algorithm which samples and filters for two consecutive S
400
signals thus increases the propagation delay through a PHY device, increasing the overall propagation delay of an S
400
transmission on the serial bus as noted above.
Additionally, according to the prior art algorithm, the port must already be receiving RX_DATA_PREFIX. Thus portRspeed cannot go valid (a speed mode cannot be validated) until one clock after portR—typically a 20 ns delay.
Accordingly, there is a need for a method and apparatus for accelerating detection of speed code signals to thereby reduce the bottleneck through a PHY device due to speed signal sampling. The present invention satisfies these needs, as well as others, and generally overcomes the deficiencies found in the background art.
An object of the invention is to provide a method and apparatus for accelerating detection of speed code signals which overcomes the deficiencies of the prior art.
Another object of the invention is to provide a method and apparatus for accelerating detection of speed code signals which reduces the propagation through a PHY device.
Another object of the invention is to provide a method and
Apple Computers Inc.
Lefkowitz Sumati
Sierra Patent Group Ltd.
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