Method and apparatus for accelerated post-silicon testing...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Event-driven

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C703S014000, C703S015000, C702S117000, C702S119000, C702S120000, C716S030000

Reexamination Certificate

active

07133818

ABSTRACT:
A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.

REFERENCES:
patent: 5923836 (1999-07-01), Barch et al.
patent: 6009256 (1999-12-01), Tseng et al.
patent: 6272451 (2001-08-01), Mason et al.
patent: 6295623 (2001-09-01), Lesmeister et al.
patent: 6975956 (2005-12-01), Chang et al.
patent: 6993694 (2006-01-01), Kapur et al.
patent: 2001/0016927 (2001-08-01), Poisner
patent: 2001/0034866 (2001-10-01), Barry et al.
patent: 2003/0229834 (2003-12-01), Cooke
patent: 2004/0059536 (2004-03-01), Chang et al.
patent: 2004/0086117 (2004-05-01), Petersen et al.
patent: 2005/0010778 (2005-01-01), Walmsley
patent: 2005/0066168 (2005-03-01), Walmsley
patent: 2005/0154948 (2005-07-01), Dervisoglu et al.
patent: 2005/0268196 (2005-12-01), Chang et al.
UK Combined Search and Examination Report dated Jul. 7, 2004 (3 pgs.).
Hayes, John, “Transistion Count of Combinational Logic Circuit”, Jun. 1976, IEEE Transactions on Computers, vol. C-25, No. 6, pp. 613-620.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for accelerated post-silicon testing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for accelerated post-silicon testing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for accelerated post-silicon testing... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3659511

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.