Method and apparatus for accelerated instruction restart in a mi

Electrical computers and digital processing systems: processing – Processing control – Branching

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G06F 940

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059448180

ABSTRACT:
A system for accelerating instruction restart in a microprocessor. An instruction is fetched. The instruction is placed in a macro-instruction queue and sent to the decoder. The instruction is decoded in order to produce at least one micro-operation. The micro-operation is executed, and the microprocessor checks for instruction restart conditions. If an instruction restart condition is found, the instruction restart function is performed. The instruction restart function includes decoding the instruction stored in the macro-instruction queue and executing the corresponding micro-operations.

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Popescu, "The Metaflow Architecture" IEEE , 1991, pp. 10-13, 63-73, Jun. 1991.

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