Method and apparatus for a zero voltage processor sleep state

Electrical computers and digital processing systems: support – Computer power control

Reexamination Certificate

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C713S320000, C713S324000, C712S028000, C714S015000

Reexamination Certificate

active

07664970

ABSTRACT:
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

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