Method and apparatus for a zero voltage processor sleep state

Details Method and apparatus for a zero voltage processor sleep state Method and apparatus for a zero voltage processor sleep state

2011-05-31

2011-05-31

Stoynov, Stefan (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

C713S320000, C713S324000, C307S018000, C307S031000, C307S058000, C307S125000, C323S371000, C363S034000, C363S059000, C363S067000, C363S074000, C365S226000

Reexamination Certificate

active

07953993

ABSTRACT:
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.

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