Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-02-05
2001-01-16
Teska, Kevin J. (Department: 2763)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C717S152000
Reexamination Certificate
active
06175948
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to electronic based product development and more particularly to a method and apparatus for providing a design process to develop equipment to meet users' communication requirements. Presently, there are communication engineers that are adept at creating the processing for various communication waveforms. After waveform functionality is determined, the next step is to reduce the requirements and design of that waveform to a target implementation or to radio equipment for proving out equipment feasibility. No low cost or quick way of performing this step is available.
Traditionally, after the communications engineer completes waveform design and validation, teams for developing software, hardware, and systems develop and integrate a full communication system before feasibility is known. Efficient generation of algorithm waveforms as applicable to communication system development requires concurrent considerations in development, hardware architecture, software architecture, and the underlying technologies. Implementations of the traditional design process do not lend themselves to this once a partitioning between hardware and software has taken place because it is very difficult to rethink or replan the initial partitioning approach without significantly increasing cost and/or increasing cycle time. Vendor products support steps of the process but do not take the full system development and implementation into consideration.
Reuse of design or portions of implementations provide an approach to reduce cost and/or schedule of product development. However, reuse of previously developed designs requires text searches and evaluations, which is very time consuming and inefficient. In addition, the reuse of design or software code may not be possible because design reuse was not addressed during development or the code is not well documented.
Another approach to improve the cycle time of development is component based software development. However, component based software development is viewed as presently being inefficient because overhead is added when modules are combined. Increasing processing overhead is especially undesirable in embedded digital signal processor application designs where speed and size are critical parameters.
Current computer aided development technology has focused on generation and optimization of hardware design synthesis rather than on software. While there are commercial efforts in this area they address part of the process of the present invention but do not provide a seamless approach to total system/software development. None of the electronic based communications development aids such as Cadence®, ALTA®, SPW®, and HDS® have component based system development for heterogeneous multi-processor systems. Additionally, none of the above development aids nor the synthesis systems such as Synopsys COSSAP® and Design Compiler® have a means to partition application functionality to a target architecture.
The primary focus of the above commercial development systems as well as ViewLogic® and ACD DSP CANVAS is the direct synthesis to hardware. Other development systems such as Mentor Graphics and DSP Station and the above systems all have synthesis to software for programmable hardware only as a secondary focus. This results in all of the presently available commercial development systems being much more inefficient than desired for software synthesis. Other drawbacks of the present technology include the lack of code optimization for such aspects as: retargeting, C, embedded, or assembly.
Accordingly, it would be advantageous to have a method and apparatus for a waveform compiler that provides waveform application development, allows partitioning of that application functionality to a target architecture, and further provides a way of generating and optimizing code and ancillary target software for use in communication systems.
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Chrulski Christopher Mark
Miller Annamarie
Bogacz Frank J.
Motorola Inc.
Teska Kevin J.
Thompson A. M.
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