Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1998-06-30
2001-01-16
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S207000, C257S679000, C257S531000
Reexamination Certificate
active
06175124
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates to an improved data processing system. More specifically, the invention relates to a semiconductor data processing system. Still more specifically, the invention relates to a data processing system using a wafer scale integrated circuit device.
2. Description of the Related Art
In manufacturing integrated circuits, one difficulty that manufacturers of integrated circuits are faced with is that with increasing functionality of integrated circuits, an increase of the complexity of the packaging required to provide mechanical protection and an interface for power and signals between the integrated circuit encapsulated in a package and other integrated circuits in other packages. Along with the increasing complexity of the package comes a problem with radiating waste heat generated by the die containing the integrated circuit encapsulated in a package.
One approach employed by manufacturers is creating an integrated circuit system using an entire wafer, rather than separating dies in the wafer, encapsulating the dies in separate packages, and placing the packaged dies on a board to create the integrated circuit system. A wafer scale integrated circuit (WSIC) device is made up of an array of undiced chips or modules. These chips or modules could include, for example, data storage circuitry (DRAM, SDRAM, etc) or digital and analog data processing circuitry (digital signal processors, microprocessors, A/D converters, etc). The ability to practically fabricate wafer scale integrated circuits has been advanced by recent improvements in overall defect levels, or yield, and in the ability to perform such post processing steps as laser trimming and fusible links. See, for example, U.S. Pat. Nos. 5,576,554 and 5,126,828. Using these techniques, nonfunctional sites can be selectively disabled. Wafer scale integrated circuits enable circuitry that operates at faster speeds, and electronic systems that occupy smaller volumes.
Otsuka, et al (U.S. Pat. No. 4,965,653) discusses several practical problems encountered in wafer scale integration. Wafer scale integrated circuits call for a significant increase in the number of data input and output channels. These are conventionally delivered using mechanical wire connections. These large number of mechanical connections, especially when compounded with an increased circuit area, gives rise to physical stresses and strains, which can deleteriously effect the delicate silicon or GaAs crystal structure.
Often the data and power wire connections are made with ball bonds, and are very large relative to other circuit feature sizes. Further, these bond pads must be made even larger than necessary, to allow for mechanical alignment tolerances in the ball bonding process. Thus, the use of a large number of wire connections provides an inefficient use of the wafer since semiconductor which could be used for logic circuitry is devoted to mechanical interconnects.
Thermal management issues also become more difficult as the area of the integrated circuitry grows. Thus heat removal becomes a challenge in wafer scale integrated circuits. If the device is insufficiently cooled, the operational characteristics deteriorate.
Therefore it would be advantageous to have an improved wafer scale integrated circuit device with improved packaging.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide an improved wafer scale integrated circuit device.
It is another object of the present invention is to eliminate ball bond type connections to and from the wafer and thereby reduce stresses in the wafer and to eliminate wasted area.
It is yet another object of the present invention to allow for improved thermal management, by separating the electrical conduction from the thermal conduction. More efficient schemes for heat removal may be used because of this invention.
It is an additional another object of the present invention to allow improved electrical isolation of the wafer scale integrated circuitry.
The present invention provides an improved wafer scale integrated circuit is described which includes non-contact power and data transmission coupling. Wireless power and data coupling reduces the mechanical stresses and strains on the wafer, and makes better use of the wafer area. An additional benefit comes from allowing better heat transfer management. In one embodiment, power is provided by inductive coupling. Data flow into and out of the wafer is accomplished optically, using optical detectors to receive and light emitting diodes to transmit. Multiple devices are integrated onto the semiconductor wafer. Systems may be incorporated using the traditional die sites. Connections between systems are made in the space between die sites.
The present invention achieves these objects along with other object that will become apparent in the following description a preferred embodiment of the present invention.
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Cole Richard K.
Rittenhouse Scott J.
Tollerud Brad S.
Von Thun Matthew S.
Yakura James P.
Hardy David
LSI Logic Corporation
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