Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1997-04-01
2000-01-11
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714758, 714781, 714807, 708492, H03M 1300
Patent
active
060147679
ABSTRACT:
A process and an apparatus to calculate the FCS (Frame Check Sequence) error checking code of packets payload sent over a fixed size packet networks in a network equipment sending said packets and to check said FCS in the network equipment receiving said packet; this invention applies to calculations of FCS based on CRC (Cyclic Redundancy Checking) codes generated by the polynomial generator of degree 10, G(X)=X.sup.10 +X.sup.9 +X.sup.5 +X.sup.4 +X+1. Particularly, this invention is for use in the ATM layer of ATM nodes processing OA&M and AAL3/4 ATM cells. The solution consists in using the calculation of the FCS based on the CRC code generated by the polynomial generator of degree 9, X.sup.9 +X.sup.4 +1 and simple operations. The calculation and the checking of the FCS is simple and thus the performance are improved authorizing the support of higher speed network lines.
REFERENCES:
patent: 5335233 (1994-08-01), Nagy
patent: 5539756 (1996-07-01), Glaise et al.
patent: 5689518 (1997-11-01), Galand et al.
patent: 5694407 (1997-12-01), Glaise
International Business Machines - Corporation
Moise Emmanuel L.
Woods Gerald R.
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