Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2004-06-09
2010-02-16
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S147000, C710S305000
Reexamination Certificate
active
07664909
ABSTRACT:
An apparatus and method is provided for allowing one or more processing complexes to share a disk controller, particularly a serial ATA (SATA) controller. Each processing complex utilizes its own load-store domain to couple to the shared SATA controller, either directly, or indirectly through a shared I/O switch. Ultimately, requests from the processing complexes are presented to the switch with operating system domain header (OSD header) information so that the shared SATA controller can determine which request came from which processing complex, and allocate resources accordingly. Upstream responses from the shared SATA controller include the OSD header so that the shared I/O switch can accurately route the responses to their respective processing complexes. The shared SATA controller includes OSD ID logic to determine the source/result of packets, one or more task files to support multiple processing complexes, and one or more DMA engines to improve performance for requests from multiple processing complexes.
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Huffman James W.
Kim Matt
Nextio Inc.
Patel Kaushikkumar
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