Method and apparatus for a reference clock buffer system

Details Method and apparatus for a reference clock buffer system Method and apparatus for a reference clock buffer system

2006-11-28

2006-11-28

Miska, Vit W. (Department: 2841)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

C326S026000, C326S032000, C327S379000, C327S563000, C330S256000, C330S257000, C330S261000

Reexamination Certificate

active

07142005

ABSTRACT:
According to one example embodiment, a buffer, e.g., in a clock/signal distribution apparatus is provided that substantially reduces jitter due to power supply noise. Decoupler and input stage isolates load from the top rail power supply (VDD). In a more particular embodiment, jitter contributions from the bottom rail power supply (VSS) can be minimized by cross-coupled load devices within load. Substantial independence from process and temperature is facilitated through the use of current bias, such as Proportional to Absolute Temperature (PTAT) current bias.

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