Method and apparatus for a RAM circuit having N-nary word line g

Details Method and apparatus for a RAM circuit having N-nary word line g Method and apparatus for a RAM circuit having N-nary word line g

1998-09-09

2000-05-30

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518908, G11C 800

Patent

active

060698365

ABSTRACT:
A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-nary, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-nary, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-nary) 1-of-N logic gate.

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