Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-06-27
2006-06-27
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S154000, C709S236000
Reexamination Certificate
active
07069407
ABSTRACT:
A method and apparatus for a multi-channel high speed framer is described. In one embodiment, the invention is an apparatus. The apparatus includes a first plurality of pipeline stages suitable for data framing between a link layer and a network interface. The apparatus also includes a first memory coupled to each pipeline stage of the first plurality of pipeline stages, the first memory to store context information at predetermined stage locations for each pipeline stage. The apparatus further includes a first control logic coupled to the first memory and to each pipeline stage of the first plurality of pipeline stages, the first control logic to control transfer of data between the first memory and the first plurality of pipeline stages. Within the apparatus, each stage of the first plurality of pipeline stages is suitable for loading the context information from the first memory through first control logic and performing a sub-function of data framing.
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Kanagaraju Ponnusamy
Vasudevan Velamur Krishnamachari
Verma Vatan Kumar
Baker Paul
Blakely , Sokoloff, Taylor & Zafman LLP
Cypress Semiconductor Corporation
Padmanabhan Mano
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