Method and apparatus for a modified parity check

Details Method and apparatus for a modified parity check Method and apparatus for a modified parity check

2007-09-25

2007-09-25

Dildine, R. Stephen (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C711S002000, C711S005000, C714S773000

Reexamination Certificate

active

10912483

ABSTRACT:
A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.

REFERENCES:
patent: 3890469 (1975-06-01), Kelly et al.
patent: 2004/0186944 (2004-09-01), Tseng et al.
patent: 2005/0188281 (2005-08-01), Nguyen et al.

Affiliated with

Also associated with

Rating

Method and apparatus for a modified parity check does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for a modified parity check, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for a modified parity check will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3721824