Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-04-07
2003-01-07
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C341S126000
Reexamination Certificate
active
06505266
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to a signal generator and more particularly to a method and apparatus for generating an analog signal from programmable data stored in a non-volatile memory of the apparatus.
BACKGROUND ART
With constant development of new process technologies for the manufacture of integrated circuits (IC), initial yields using these new process technologies are often less than desired. Many times, the defective ICs are fully functional except for certain sections of the ICs where data cells are damaged. Memory ICs in particular exhibit these kinds of register flaws.
Various techniques have been developed to deal with the flaws in the data cells. These techniques include setting aside extra registers in a memory IC during fabrication so that damaged sections of data cells can be reassigned to the extra registers. However, drawbacks with this technique include loss of die space that could be used for cell circuitry and a reduction in the number of components that are fabricated per square inch of die material. Moreover, there will always be instances when the number of registers set aside in anticipation of flawed data cells are not enough to cover the defective data cells.
Non-volatile memory, a special type of memory that is less widely used and much more expensive to manufacture than a typical random access memory (RAM) also experiences flaws associated with register damage during manufacture. Non-volatile memory has properties that enable the memory to be rewriteable and to retain its data even after power is removed from the memory. It is of particular value in applications where an electronic device must be turned off as in the case of digital cameras, video cameras, and other re-recordable audio and graphic capture devices.
In general, during the manufacture of IC devices, quality control for the completed ICs entails a series of verification tests that are designed to exercise the electronic circuitry of an IC. If the IC passes the verification tests, it is deemed good and packaged. If the IC fails a verification test, it is deemed bad and disposed. In the case of IC manufacturing of non-volatile memory such a s Flash memory or EEPROM (electrically erasable programmable read only memory), the process technology requires additional processing steps. The manufacturing costs of the increased processing steps add to the price of the non-volatile memory and cause much disparity between the price of nonvolatile memory and RAM. Thus, merely disposing a completed but defective nonvolatile memory IC because it did not pass a suite of quality control tests is not cost effective and becomes expensive. Particularly if the failure pertains to limited failures to sections of the data cells within the non-volatile memory.
Therefore, there is a need to develop practical applications for using ICs that are found to exhibit data cell failures.
DISCLOSURE OF THE INVENTION
The present invention provides an apparatus and a method for generating an analog signal from programmed digital data. The novel improved apparatus for generating an analog signal is based on an ability to use an IC memory that may exhibit errors in its data cells and programming the IC memory with digital data and converting the digital data to an analog signal. Thus, according to one aspect of the invention, the apparatus for generating an analog signal comprises an I
2
C interface configured to provide programming data in response to write control signals, a non-volatile memory coupled to the I
2
C interface configured to store the programming data, a pulse width modulator coupled to the non-volatile memory configured to receive the programming data from the non-volatile memory and provide a pulse width modulated output in response to the programming data, and a d/a converter coupled to the non-volatile memory configured to receive the programming data from the non-volatile memory and provide an analog output in response to the programming data.
According to another aspect of the invention, a piezoelectric speaker is coupled to the pulse width modulator configured to produce audible sound. The I
2
C interface receives read control signals to access the programming data stored in the non-volatile memory for output to the pulse width modulator. The pulse width modulator includes a first output pin and a second output pin coupled the piezoelectric speaker. The non-volatile memory may have data cell errors; however, even with data cell errors, the programmed data from the non-volatile memory still produces quality sound. Thus, even if the non-volatile memory may not have passed verification tests, the data cell errors do not adversely affect the sound produced from the piezoelectric speaker. The flawed non-volatile memory devices can be acquired at a reduced cost and when combined with an I
2
C interface and a PWM, the assembly provides a low cost re-recordable audio sound generator.
According to another aspect of the invention, a dynamic speaker is coupled to the d/a converter configured to produce audible sound. The I
2
C interface receives read control signals to access the programming data stored in the non-volatile memory for output to the d/a converter. Similarly to the piezoelectric speaker, data cell errors do not adversely affect the sound produced from the dynamic speaker. Human hearing is not sufficiently acute to perceive the data cell errors once the programming data in digital form is converted to analog form for output to the dynamic or piezoelectric speaker.
According to another aspect of the invention, the I
2
C interface includes a chip select configured to receive a chip select signal to activate the I
2
C interface. Multiple signal generator devices can be cascaded to provide extended storage of programming data.
REFERENCES:
patent: 4933675 (1990-06-01), Beard
patent: 4947171 (1990-08-01), Pfeifer et al.
patent: 5664218 (1997-09-01), Kim et al.
patent: 6232899 (2001-05-01), Craven
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