Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1997-11-26
2001-04-03
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S105000, C365S226000, C365S227000, C713S001000
Reexamination Certificate
active
06212599
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer systems, and more specifically, to power management in a computer system.
BACKGROUND OF THE INVENTION
Many of today's computer systems are mobile. In mobile computer systems, the control of the computer system may be split up between a main processor and a mobile system controller. The mobile system controller may control a dynamic memory and a cache.
Such mobile computer systems are generally powered by batteries at least some of the time. Users expect to use their mobile computer for a long time without recharging the batteries. Today's mobile computer systems extend battery life by creating more powerful batteries and/or by decreasing power consumption of the mobile computer system. One method of decreasing the power consumption of the computer system is to have a sleep mode.
The sleep mode involves turning off the power to at least some of the components of the computer system, thereby decreasing power consumption and increasing battery life. However, dynamic memory in the computer system has to be maintained even when the computer system is in sleep mode. The memory used in the computer system may be synchronous dynamic random access memory (SDRAM), extended data out random access memory (EDO DRAM), fast page mode (FPM) DRAM, or another type of dynamic random access memory (DRAM). All of these types of DRAM need be periodically refreshed in order to maintain the data values stored in them. In non-self-refresh type of DRAM, the system clock has to provide refresh signals to the DRAM. However, the system clock consumes power.
Some types of DRAM, including SDRAM, are able to execute self-refresh cycles. In the self-refresh cycle, the DRAM uses an internal clocking to refresh itself, and no external clocks are required. In these types of DRAM, power consumption is reduced by shutting off the system clock. Once the DRAM is placed into the self-refresh mode using a self-refresh command, the system clock may be turned off.
However, the memory controller needs to remain powered, to maintain the DRAM in the self-refresh mode and in order to exit from the self-refresh mode. Furthermore, if EDO DRAM is also included in the system, the system clock is needed to time refresh cycles for the EDO DRAM. The memory controller consumes power, as does the system clock. Because extending battery life is a goal, a system that permits reduction of the power consumed by the computer system during sleep mode is advantageous.
SUMMARY OF THE INVENTION
The present invention is a memory control system. The memory control system includes a first memory controller designed to access and refresh a DRAM using a clock, during a first operation mode. The memory control system further includes a suspend memory controller designed to maintain the DRAM during a second operation mode and to exit from the second operation mode. During the second operation mode the clock or both the clock and power are turned off to the first memory controller. Upon returning to the first operation mode from the second operation mode, the first memory controller does not need to be initialized again. Since a significant proportion of the power is consumed by the first memory controller, power consumption is reduced during the second operation mode using this system.
The present memory control system may support synchronous dynamic random access memory (SDRAM).
The present memory control system may also support both types of memory, SDRAM and EDO DRAM.
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Baweja Gunjeet
Misra Navin
Bataille Pierre-Michel
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Thai Tuan V.
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