Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-10-30
2001-10-02
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S149000
Reexamination Certificate
active
06298105
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a computer clock network and, more particularly, to a method and apparatus for a low skew, low standby power clock network for a synchronous digital system (e.g., a microprocessor) using hybrid clock deskewing elements and low latency deskewing logic.
2. Description of the Related Art
The clock speed of microprocessors has increased dramatically over the past several years. In the early eighties, microprocessors had clock speeds typically ranging from 5 to 16 MHz, which was sufficient to handle computer applications during that time period. However, as computer applications became more complex over the years to meet the demands of the computer user, the sluggish processor speeds of the past did not suffice. Today, microprocessors have clock speeds far exceeding those of the past, running at more than 300 MHz. And, these clock speeds show no sign of reaching a pinnacle. The microprocessors of the not-to-distant future have projected clock speeds that will significantly dwarf today's clock speed standards. With these higher clock speeds, microprocessors are capable of handling more and more complex computer applications in shorter periods of time, thus providing inherent benefits to the computer user.
Currently, a microprocessor's clock speed is limited by clock skew. Clock skew is a phenomenon in which certain operational factors of the microprocessor affect the arrival times of clock pulses to its various processing components (e.g., flip-flops). Such operational factors could be, for example, voltage or temperature variations on the microprocessor chip.
As the clock speeds of these microprocessors increase, their clock cycles decrease, thus causing the clock pulses to occur more frequently. As a result of the shorter clock cycles, clock skew management becomes more important because clock skew has a much greater impact on these shorter clock cycles. That is, a clock skew of 30 picoseconds would have more of an effect on a shorter clock cycle of 1 nanosecond (of a higher-speed processor) than it would on a longer clock cycle of 4 nanoseconds (of a lower-speed processor), for example. Accordingly, the maximum operating potential of these higher-speed microprocessors may not be achieved as a result of the profound impact of clock skew on these shorter clock cycles.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a clock network for a synchronous digital system is provided. The clock network comprises a reference network, which maintains a reference clock signal and a plurality of clock spines, with each clock spine maintaining a respective spine clock signal. The clock network further comprises phase relation extraction logic that compares the phase relationships of the reference clock signal with the phase relationships of the spine clock signals. The phase relation extraction logic further adjusts the phase relationships of the spine clock signals in response to the comparison of the phase relationships.
In another aspect of the present invention, a method is provided for reducing clock skew in a clock network. A reference clock signal and a plurality of spine clock signals are provided. It is determined if the phase of the reference clock signal matches the phases of said spine clock signals. If the phases do not match, the phases of the spine clock signals are adjusted.
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Dai Xia
Geannopuolos George
Orton John
Taylor Greg F.
Wong Keng
Blakely , Sokoloff, Taylor & Zafman LLP
Corrielus Jean B
Intel Corporation
Pham Chi
LandOfFree
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