Method and apparatus for a low power self test of a memory subsy

Details Method and apparatus for a low power self test of a memory subsy Method and apparatus for a low power self test of a memory subsy

1998-06-10

2000-05-23

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714733, 36518901, 365194, 365201, 365233, G11C 2900, G01R 3128

Patent

active

060676493

ABSTRACT:
A technique self tests a memory system having memory modules that operate at a normal operating clock rate during a normal operating mode. Each memory module has multiple arrays of synchronous dynamic random access memory devices. The technique involves obtaining, independently of a central controller, time phase identifiers that respectively correspond to the memory modules, and reducing the normal operating clock rate to a reduced clock rate. The technique further involves executing, in the memory modules, self test transactions in different time phases depending on the obtained time phase identifiers. The memory modules initiate execution of self test transactions at the reduced clock rate. Multiple memory modules execute self test transactions in each of the different time phases. Each memory module executes self test transactions that alternately access the multiple arrays of that memory module. Preferably, the time phase identifiers are based on module identifiers that uniquely identify the memory modules.

REFERENCES:
patent: 5216672 (1993-06-01), Tatosian et al.
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5539692 (1996-07-01), Kajigaya et al.
patent: 5553082 (1996-09-01), Connor et al.
patent: 5587950 (1996-12-01), Sawada et al.
patent: 5995424 (1999-11-01), Lawrence et al.
Product Specification: KM48S8030/KM48S8031, Target/CMOS SDRAM, 8M.times.8 BIT Synchronous Dynamic RAM, Rev. 0, Samsung Electronics.

Affiliated with

Also associated with

Rating

Method and apparatus for a low power self test of a memory subsy does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for a low power self test of a memory subsy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for a low power self test of a memory subsy will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1844978