Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-12-20
2003-09-09
Cho, James (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S031000
Reexamination Certificate
active
06617880
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to I/O (input/output) signal to signal coupling resulting from simultaneous switching output (SSO) switching. In particular, the present invention relates to an a method and apparatus for a low power, multi-mode GTL interface signaling buffer utilizing midrail buffer pad clamping.
BACKGROUND OF THE INVENTION
FIG. 1A
depicts a block diagram of a computer system
100
including a chipset
102
having a plurality of front side buses (FSB) buffers
104
(
104
-
1
,
104
-
2
, . . . ,
104
-N) each attached to a corresponding chipset FSB
106
(
106
-
1
,
106
-
2
, . . . ,
106
-N). The computer system
100
further includes a CPU
110
including a plurality of FSB buffers
112
(
112
-
1
,
112
-
2
, . . . ,
112
-N), each attached to a corresponding CPU FSB
114
(
114
-
1
,
114
-
2
, . . . ,
114
-N). Each respective chipset FSB
106
communicates with a corresponding CPU FSB
114
via a trace/lane
120
(
120
-
1
,
120
-
2
, . . . ,
120
-N). Unfortunately, due to the growing demand for more compact, high speed circuits, VLSI (very light scale integration) designers are forced to continuously reduce the circuit area. As a result, trace lengths and distances are continuously decreasing in comparison to one another that data on these traces begin cross-coupling to each other.
For example, in the computer system
100
, the chipset
102
maybe performing simultaneous switching output (SSO), in which all buffers
104
switch simultaneously. As a result, I/O signal to signal cross-couplings between the individual traces
120
can result. Referring again to
FIG. 1A
, lane
120
-
2
may contain a pulse
122
-
2
that is moving in opposite direction as compared to pulse
122
-
1
in lane
120
-
1
, and pulse
122
-
3
in lane
120
-
3
. As a result of cross-coupling between the lanes
120
, as depicted in
FIG. 1A
, the pulse signal
122
-
2
may fail to rise to a minimum voltage level
126
as depicted in FIG.
1
B. Due to the failure of the pulse
122
-
2
to rise to the minimum voltage level
126
, as a result of cross-coupling, the CPU
110
may fail to recognize the pulse
122
-
2
as a valid rising signal transition from zero to one.
In modern gunning transistor logic (GTL) buffer design, the buffers normally include an ability to jump start a buffer pad if the chipset, for example chipset
102
, fails to generate a valid rising signal transition from zero to one. This ability to jump start the buffer pad is generally provided by a jump start device called a P-kicker device, as known to those in the art. Referring to
FIG. 1B
, a pulse signal
130
is depicted, which illustrates the pulse signal
122
-
2
after being kicked by a P-kicker device to generate an intended overshoot level
132
. Unfortunately, the CPU
110
may be an advanced process, such as a 0.85 or 0.25 micron process. As a result, the CPU
110
may have a gate oxide device thickness and voltage tolerance level, which is less than the intended overshoot level
132
. The CPU
110
gate oxide device tolerance provides a limit to the overshoot level generated by a P-kicker device.
For example, referring to the pulse
140
as depicted in
FIG. 1B
, the intended overshoot level
132
may exceed a CPU accepted overshoot level
142
. Consequently, if the P-kicker signal pulse
140
rises to an intended overshoot level
132
, in excess of the CPU accepted overshoot
142
, the signal pulse
140
will eventually break down the oxide thickness of the CPU gate oxide. This will lead to reliability problems in the CPU device
110
, resulting in a gradual break down of the gate oxide and the sudden failure of the CPU device
110
. For the reasons described above, the risk of intended overshoot levels
132
in excess of CPU accepted overshoot levels
142
is very likely to occur due to the ongoing demand for reduction of circuit area in VSLI design.
Therefore, there remains a need to overcome one or more of the limitations in the above described existing art.
REFERENCES:
patent: 5534811 (1996-07-01), Gist et al.
patent: 5576635 (1996-11-01), Partovi et al.
patent: 6288962 (2001-09-01), Nagaoka
patent: 2002/0078389 (2002-06-01), Yuan
Blakely , Sokoloff, Taylor & Zafman LLP
Cho James
Intel Corporation
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