Method and apparatus for a low latency source-synchronous...

Details Method and apparatus for a low latency source-synchronous... Method and apparatus for a low latency source-synchronous...

2005-07-05

2005-07-05

Anderson, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

C711S220000, C365S230080, C365S230090

Reexamination Certificate

active

06915407

ABSTRACT:
A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.

REFERENCES:
patent: 4701841 (1987-10-01), Goodrich et al.
patent: 5734849 (1998-03-01), Butcher
patent: 6061293 (2000-05-01), Miller et al.
patent: 6385710 (2002-05-01), Goldman et al.

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