Electrical computers and digital processing systems: memory – Address formation – Address multiplexing or address bus manipulation
Reexamination Certificate
2000-09-20
2004-06-08
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address multiplexing or address bus manipulation
C711S200000, C365S230080, C365S230090
Reexamination Certificate
active
06748513
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory controllers. In particular, the present invention relates to an apparatus and method for a low latency source-synchronous address receiver for a system bus in a memory controller.
BACKGROUND OF THE INVENTION
FIG. 1
depicts a conventional memory controller architecture system
100
. The memory controller architecture
100
generally includes a CPU
102
, a chipset
104
and a main memory
106
. The CPU
102
is coupled to the chipset
104
by a host system bus
110
while the main memory
106
is coupled to the chipset
104
by a memory bus
108
. The chipset
104
receives data requests from the CPU
102
including address packets
122
received on the host system bus
110
. Once the address packet is received by the chipset
104
, the chipset
104
decodes the address packet
122
in order to generate an address of the requested data in main memory
106
and return the requested data to the CPU
102
.
The host system bus
110
which connects the CPU
102
to the chipset
104
is generally controlled by a common clock interface. In other words, the speed at which the host system bus
110
can run is limited by the speed of the system clock, which generally runs at 100 megahertz or 133 megahertz. As technology pushes the processing speed of CPUs, such as CPU
102
, common clock interface buses, such as the host system bus
110
, run the risk of creating a bottleneck in memory controller architectures, such as the memory controller architecture
100
as depicted in FIG.
1
. In fact, these advances in processor design have pushed memory controller systems to a level where the speed of a bus or an architecture cannot be scaled using an increased clock frequency. One technique for accommodating the increased processor speed of a CPU, such as CPU
102
, is to replace the host system bus
110
with a source synchronous system bus.
Unfortunately phase zero information (not shown) of the address packet
122
is vital for decoding of the address packet
122
by the chipset
104
. However, a memory controller system, such as a memory controller system
100
as depicted in
FIG. 1
, requires a low latency path between the system bus
110
address input to the memory bus
108
for high performance. Unless the phase zero address information can be instantly provided to the core chipset logic
104
once the address packet appears on an address pin, any benefits provided by using a source synchronous host system bus are lost.
REFERENCES:
patent: 6061293 (2000-05-01), Miller et al.
patent: 6385710 (2002-05-01), Goldman et al.
Bogin Zohar
Garcia Serafin
Rajappa Srinivasan T.
Subramanian Rajagopal
Trivedi Romesh B.
Patel H. B.
Thai Tuan V.
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