Method and apparatus for a high speed cyclical redundancy check

Details Method and apparatus for a high speed cyclical redundancy check Method and apparatus for a high speed cyclical redundancy check

1997-04-17

1999-10-12

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714757, H03M 1300

Patent

active

059648961

ABSTRACT:
A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle.

REFERENCES:
patent: 5241546 (1993-08-01), Peterson et al.
patent: 5553067 (1996-09-01), Walker et al.
patent: 5602828 (1997-02-01), Engdahl et al.
patent: 5602857 (1997-02-01), Zook et al.
"High Speed Parallel cyclic Redundancy Check Generator", IBM Technical Disclosure Bulletin, vol. 33, No. 5, pp. 51-56, (Oct. 1990).
"Parallel Checksum Calculation Accelerator", IBM Technical Disclosure Bulletin, vol. 36, No. 12, pp. 647-648, (Dec. 1993).
Johnson, B.W., "Design and Analysis of Fault-Tolerant Digital Systems", Addison-Wesley Series in Electrical and Computer Engineering, pp. 102-113, (1957).

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