Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-03-05
2001-05-15
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S200000, C711S202000, C711S206000
Reexamination Certificate
active
06233667
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to memory management units for converting virtual addresses to physical addresses in computer systems. More particularly, the present invention relates to a simple, efficient and fast method and apparatus for converting virtual addresses to physical addresses that provides protection from illegal memory accesses.
2. Related Art
Modem computer systems typically include hardware and operating system mechanisms to support memory management functions, such as virtual memory and paging. Over the years these systems have grown in complexity to include hardware structures such as memory management units (MMUs) and translation lookaside buffers (TLBs) as well as corresponding operating system mechanisms to support virtual memory and paging.
This memory management circuitry presently comprises a significant portion of the computational circuitry in a computer system. Consequently, the task of designing this memory management circuitry consumes a great deal of engineering resources, which increases the time and expense involved in developing a computer system. Furthermore, integrating this additional memory management circuitry onto a semiconductor chip increases the die size of the chip. This can lower yield during chip fabrication, which can greatly increase system cost. The additional circuitry also requires circuit signals to traverse larger distances, which can reduce processor clock speeds or result in increased latencies for memory accesses, and thereby reduce system performance. This results in increased latencies for memory accesses. Conventional memory management units also typically include circuitry to implement content addressable memories (CAMs) which consume a great deal of power.
Memory management functions also comprise a significant portion of the code in an operating system, which can greatly increase the complexity of the operating system. This correspondingly increases the amount of time and expense involved in developing the operating system.
Furthermore, the performance advantages of paging mechanisms are somewhat diminished for programs written in modem object-oriented programming languages. References to objects tend to be widely dispersed across a large number of pages. Consequently, such object-oriented programs tend to exhibit poor paging performance.
What is needed is a memory management mechanism that eliminates the complexity of conventional virtual memory paging systems.
SUMMARY
The present invention provides a method and an apparatus for translating a virtual address to a physical address in a computer system. The system receives a virtual address during an execution or a fetch of a program instruction. The system determines if the virtual address is in an upper portion or a lower portion of a virtual address space. If the virtual address is in the lower portion of the virtual address space, the system adds the virtual address to a first base address to produce the physical address. The system also compares the virtual address against an upper bound. If the virtual address has a larger value than the upper bound, the system indicates an illegal access. If the virtual address is in the upper portion of the virtual address space, the system adds the virtual address to a second base address to produce the physical address. The system also compares the virtual address against a lower bound. If the virtual address has a lower value than the lower bound, the system indicates that the access is illegal. Thus, the system provides protection from illegal memory accesses. According to one aspect of the present invention, the system determines if the virtual address falls within a portion of the virtual address space that is protected from write accesses. If so, the system disallows write accesses to the virtual address. Thus, the present invention dispenses with paging and reduces the virtual-to-physical address translation process to a simple addition operation. This leads to faster processor clock speeds, and can greatly reduce the cost of designing and fabricating a computer system.
REFERENCES:
patent: 3803559 (1974-04-01), Bandoo et al.
patent: 4837738 (1989-06-01), Lemay et al.
patent: 4926322 (1990-05-01), Stimac et al.
patent: 5420993 (1995-05-01), Smith et al.
patent: 5509131 (1996-04-01), Smith et al.
patent: 5555395 (1996-09-01), Parks
patent: 5687342 (1997-11-01), Kass
patent: 5696927 (1997-12-01), MacDonald et al.
patent: 5854913 (1998-12-01), Goetz et al.
patent: 5901246 (1999-05-01), Hoffberg et al.
patent: 6081750 (2000-06-01), Hoffberg et al.
patent: 0 656 592 A1 (1994-11-01), None
patent: 2 766 597 (1999-01-01), None
Chan Jeffrey M. W.
Oblock Gary R.
Shaylor Nik
Tremblay Marc
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
Thai Tuan V.
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