Boots – shoes – and leggings
Patent
1994-10-11
1996-07-16
Heckler, Thomas M.
Boots, shoes, and leggings
364DIG1, 3642689, 364270, G06F 104, G06F 1120
Patent
active
055375839
ABSTRACT:
A fail-operational/fail-operational fault tolerant clock includes a voting core comprised of triple redundant clock modules (30, 40, 50) and a floating hot spare module (60). Each module includes a voter (84) and fault detection, identification and reconfiguration circuitry (82) which operates to substitute the floating hot spare module produced clock signal for a failed voting core module signal without the introduction of transients or an asynchronous voted output. The modules (30, 40, 50, 60) are all preferably formed on a single semiconductor chip which includes isolation guard rings (32, 42, 52, 62) and independent power leads (34, 44, 54, 64) in addition to isolation buffering and point-to-point wiring to enhance fault tolerance.
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VanAlen et al.; "An All Digital Phase Locked Loop Fault Tolerant Clock"; IEEE Inter-Symposium on Circuit C System; Apr. 4, 1991; pp. 3170-3173.
Hamley James P.
Heckler Thomas M.
The Boeing Company
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