Method for improving the planarity and passivation in a semicond

Details Method for improving the planarity and passivation in a semicond Method for improving the planarity and passivation in a semicond

1984-06-29

1987-05-12

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29576E, 29576B, 148187, 156643, 156644, 357 50, 357 91, H01L 21302, H01L 2176, H01L 21306

Patent

active

046638326

ABSTRACT:
In a semiconductor substrate having a trench isolation pattern formed therein, a method is taught for improving the planarity of the substrate and for improving the silicon nitride passivation at the trench peripheries. The quality of the trench edge is improved by providing for an undercut silicon dioxide layer and a recessed silicon sidewall arrangement below the silicon nitride layers resulting in better protection of the underlying SiO.sub.2 and Si regions. In further processing, improved planarity between the polyimide-filled trench and the adjacent substrate is achieved by establishing a polyimide etch-back point via a previously deposited oxide layer. Subsequent removal of the oxide does not affect the polyimide; the top of said polyimide being substantially planar with the adjacent substrate.

REFERENCES:
patent: 433794 (1982-06-01), Beyer et al.
patent: 4271583 (1981-06-01), Kahng et al.
patent: 4391033 (1983-07-01), Shinozaki
patent: 4396460 (1983-08-01), Tamaki et al.
patent: 4419813 (1983-12-01), Iwai
patent: 4443933 (1984-04-01), De Brebisson
patent: 4466180 (1984-08-01), Soclof
patent: 4493740 (1985-01-01), Komeda
patent: 4502914 (1985-03-01), Trumpp et al.

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