Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2000-02-10
2002-06-18
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S028000, C326S112000
Reexamination Certificate
active
06407585
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to dynamic logic circuits. More particularly, the invention relates to a new family of self-clocked dynamic logic gates.
BACKGROUND OF THE INVENTION
A static logic gate is a fully complementary logic gate having both PMOS and NMOS devices configured to implement a desired function. Typically, each NMOS device is accompanied by a corresponding PMOS device. In this way, a static CMOS gate is expensive to implement and requires significant die space.
A dynamic logic gate consists of a structure having a single output node and any number of NMOS devices coupled to the output node for conditionally discharging the output node to a low voltage rail Vss depending upon inputs to the NMOS devices. A dynamic logic gate also includes at least one PMOS device which is coupled to the output node for precharging the output node to a high voltage rail Vcc. The PMOS device has a gate coupled to a clock signal, a source coupled to the high voltage rail and a drain coupled to the output node. When the clock signal is low, the PMOS device is turned on and the output node is precharged and driven to the high voltage rail Vcc. When the clock signal is high, the logic gate is evaluated. If the inputs which are coupled to the gates of the NMOS transistors become high, the output node is conditionally discharged (evaluated) through the NMOS devices to the low voltage rail Vss.
A conventional dynamic logic circuit usually includes multiple dynamic logic gates which are arranged in a plurality of stages, wherein the operation of each gate in the unit is controlled by the clock signal and the outputs from the prior stage. In this arrangement, input signals applied to a first stage while the clock signal is active trigger operation of the remaining stages in sequence, yielding a domino-like signal propagation through the conventional dynamic logic circuit. Hence, the term “domino” logic is often used in describing such circuits. In a conventional “domino” logic circuit each of the stages are coupled to the clock signal and are precharged when the clock signal is low.
FIG. 1
illustrates a domino logic circuit having a first stage dynamic AND gate coupled to a second stage NAND gate. The first stage dynamic AND gate is designated by the broken lines
100
and the second stage dynamic NAND gate is designated by the broken lines
200
in FIG.
1
. The first stage dynamic AND gate
100
includes a PMOS transistor
110
having a gate coupled to a clock signal CLK, a source coupled to a high voltage rail V
DD
, and a drain coupled to an output node
120
. The drain of the PMOS transistor
110
is also coupled to a drain of first NMOS transistor
130
. A gate of the first NMOS transistor
130
is coupled to receive an input signal A and a source of first NMOS transistor
130
is coupled to a drain of a second NMOS transistor
140
. A gate of the second NMOS transistor
140
is coupled to receive an input signal B and a source of the second NMOS transistor
140
is coupled to a drain of a third NMOS transistor
150
. A gate of the third NMOS transistor
150
is coupled to receive the clock signal CLK and a source of the third NMOS transistor
150
is coupled to a low voltage rail Vss. The output node
120
is coupled to an input of an inverter
160
, having an output O
1
. The output O
1
is the output from the first stage dynamic AND gate
100
.
In operation, when the clock signal CLK is inactive (low), then the PMOS transistor
110
is on and the third NMOS transistor
150
is off. In this state, the output node
120
is precharged to the high voltage rail V
DD
and the output O
1
of the inverter
160
is driven low. Accordingly, the output O
1
from the first stage dynamic AND gate
100
is initially driven low during precharge between each evaluate cycle. When the clock signal goes active (high), the PMOS transistor
110
turns off and the third NMOS transistor
150
turns on. This allows the voltage at the output node
120
to be evaluated or selectively discharged depending upon the inputs A and B. If the voltages at the inputs A and B are both high, then both the first and second NMOS transistors
130
and
140
will turn on. When this occurs, the voltage at the output node
120
drops to the low voltage rail Vss and the output O
1
of the inverter
160
is driven high. If only one of the inputs A or B is high, while the other is low, then both the first and second NMOS transistors
130
and
140
will not turn on (only one of the transistors will turn on while the other will remain off), in which case the voltage at the output node
120
will remain at the high voltage rail V
DD
and the output O
1
from the inverter
160
will remain low. Accordingly, only when the voltages at both inputs A and B are both high during the evaluate cycle will the output from the inverter
160
be driven high.
The first stage dynamic AND gate
100
also, optionally, includes a feedback circuit which is designated by the broken lines
170
in FIG.
1
. The feedback circuit
170
is comprised of a PMOS transistor
180
having a source coupled to the high voltage rail V
DD
, a drain coupled to the output node
120
, and a gate coupled to the output O
1
of the inverter
160
. Over time, the precharge voltage at the output node
120
may drop due to leakage of through current which may be caused if noise at the inputs A and B inadvertently activate the NMOS transistors
130
and
140
. If the voltage at the output node
120
were to drop below a certain level due to leakage of through current through transistors
130
,
140
and
150
, this would cause the output O
1
at the inverter
160
to change to a “false” high, thereby effecting the entire circuit. The feedback circuit
170
is used to keep the voltage at the output node
120
stable until the inputs are all valid, thereby ensuring that the voltage at the output O
1
of the inverter
160
remains low until the inputs A and B are both high.
As indicated earlier, in the domino logic shown in
FIG. 1
, a second stage dynamic NAND gate
200
is coupled to the first stage dynamic AND gate
100
. The second stage dynamic NAND gate
200
includes a PMOS transistor
210
having a gate coupled to the output of a delay circuit
280
, a source coupled to the high voltage rail V
DD
, and a drain coupled to an output node
220
. Typically, the delay circuit
280
is designed to receive the incoming clock signal CLK and delay the falling edge of the incoming clock signal CLK during the precharge phase. The falling edge of the clock signal is delayed a sufficient period of time until the output O
1
from the first stage dynamic AND gate
100
is switched low (the output O
1
from the first stage dynamic AND gate is switched low once the voltage at node
120
has been sufficiently precharged toward the high voltage rail V
DD
(thereby activating the inverter
160
and inverting the voltage at the output node O
1
back toward the low voltage rail Vss.
The drain of the PMOS transistor
210
is also coupled to a drain of an NMOS transistor
230
. A gate of the NMOS transistor
230
is coupled to receive the output O
1
from the first stage dynamic AND gate
100
and a source of the NMOS transistor
230
is coupled to a drain of an NMOS transistor
240
. A gate of the NMOS transistor
240
is coupled to receive an input signal C and a source of the NMOS transistor
240
is coupled to the low voltage rail. It is noted that the second stage is commonly referred to as a “footless” dynamic logic circuit since no additional clock controlled NMOS transistor is utilized during the evaluate cycle.
During the precharge stage, the delayed clock signal CLK′ is inactive and, the PMOS transistor
210
is active, thereby precharging the voltage at node
120
to the high voltage rail V
DD
. During evaluation, if the output O
1
from the first stage AND gate
100
is high and the input C to the second stage NAND gate
200
is also high, then both NMOS transistors
230
and
240
turn on. When this occurs the voltage at the output node
220
dr
Fenwick & West LLP
Fujitsu Ltd.
Le Don Phu
LandOfFree
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