Method and apparatus for a dummy SRAM cell

Details Method and apparatus for a dummy SRAM cell Method and apparatus for a dummy SRAM cell

2008-05-20

2008-05-20

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S214000, C365S189090

Reexamination Certificate

active

07376032

ABSTRACT:
A dummy SRAM cell for use in a dummy bit line circuit uses the same transistors as used in a standard SRAM cell, which includes first and second subsets of transistors configured as first and second bit line output circuits. The dummy SRAM cell includes the same first and second subsets of transistors, with the first transistors configured as a dummy bit line output circuit having substantially the same electrical characteristics as the first bit line output circuit of the standard SRAM cell. Further, the second transistors, which are not otherwise needed for the dummy SRAM cell function, are reconfigured as a voltage tie circuit for the dummy bit line output. Using the second transistors for this purpose obviates the need to add additional transistors to form a voltage tie circuit for configuring the dummy bit line output circuit as a load or driver for the dummy bit line.

REFERENCES:
patent: 5091879 (1992-02-01), Tran
patent: 6373745 (2002-04-01), Saito et al.
patent: 6717842 (2004-04-01), Watanabe et al.
patent: 7161859 (2007-01-01), Sumitani et al.
patent: 2004/0027852 (2004-02-01), Watanabe et al.
patent: 2007/0263447 (2007-11-01), Koike et al.

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