Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-22
2006-08-22
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07096437
ABSTRACT:
A dynamically configurable logic gate can include a controller configured to provide a first threshold reference signal; an adder configured to sum the first threshold reference signal and at least one input signal to generate a summed signal; a chaotic updater configured to apply a nonlinear function to the summed signal; and a subtractor configured to determine an output signal by taking a difference between a second threshold reference signal and the processed summed signal from the chaotic updater. The logic gate can operate as one of a plurality of different logic gates responsive to adjusting at least one of the threshold reference signals.
REFERENCES:
patent: 3473160 (1969-10-01), Wahistrom
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5291555 (1994-03-01), Cuomo et al.
patent: 5745655 (1998-04-01), Chung et al.
patent: 5809009 (1998-09-01), Matsuoka et al.
patent: RE35977 (1998-12-01), Cliff et al.
patent: 6025735 (2000-02-01), Gardner et al.
patent: 6876232 (2005-04-01), Yoo
patent: 2004/0036636 (2004-02-01), Mai et al.
Murali et al., “Realization of the fundamental NOR gate using a chaotic circuit,” Physical Review 68:1-5, 2003.
Murali et al., “Implementation of NOR Gate by A Chaotic Chua's Circuit,” Unpublished.
Munakata et al., “Chaos Computing: Implementation of Fundamental Logical Gates by Chaotic Elements,” IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications 49:1629-1633, 2002.
Murali et al., “Experimental Chaos Computing,” Submitted to IEEE Trans. on Circuits and Systems, in 2003.
Ditto William L.
Murali Krishnamurthy
Sinha Sudeshna
Akerman & Senterfitt
Do Thuan
University of Florida Research Foundation Inc.
LandOfFree
Method and apparatus for a chaotic computing module using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for a chaotic computing module using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for a chaotic computing module using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3714712