Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-01-11
2005-01-11
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S005000, C711S167000, C711S169000, C711S173000, C710S035000, C710S036000, C710S037000, C710S039000, C710S052000, C710S058000, C365S189040, C365S194000, C365S203000
Reexamination Certificate
active
06842837
ABSTRACT:
A method and apparatus for a burst mode write in a shared bus architecture comprising detecting a write data burst, determining if at least one memory unit is available to receive the write data burst, writing the write data burst to the at least one memory unit if the at least one memory unit is available to receive data. Storing a first portion of the write data burst in a buffer, concurrently with activating the at least one memory unit to receive data, if the at least one memory unit is not available to receive data; writing a second portion of the write data burst to the at least one memory unit when the at least one memory unit is available to receive data, and writing the first portion of the write data burst from the buffer to the at least one memory unit after writing the second portion of the write data burst.
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Peting Mark
Vanderschoot Hens
Christensen Kory D.
Digeo, Inc.
Kim Matthew
Li Zhuo H.
Stoel Rives LLP
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